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44-Pin Demo Board Lessons
FIGURE 3-7:
TIMER0 SIMPLIFIED
Clock/4 or
T0CKI pin
Prescaler
Prescaler may be configured
to divide by 2, 4, 8, 16, 32, 64,
128 or 256.
TMR0
T0IF
Flag set when
TMR0 overflows.
Must be cleared
in software.
TMR0 is a Special Function Register (SFR) and may be read or modified by the pro-
gram. The prescaler is not a SFR and thus cannot be read or modified by the program.
However, writing to TMR0 clears the prescaler.
The timer may be fed either by the same clock that drives the processor or by an exter-
nal event. Driven by the processor clock, it increments once for every instruction cycle.
This is a convenient method of marking time and is better than delay loops, as it allows
the processor to work on the problem rather than waste cycles in delay loops.
FIGURE 3-8:
PRESCALER CONFIGURATION THROUGH OPTION_REG
X
X
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
Legend:
X:
Don’t cares – not Timer0 related.
bit 0
T0CS: Timer0 Clock Source 0 for Instruction Clock.
T0SE: Timer0 Source Edge – Don’t care when connected to instruction clock.
PSA:
PS:
Prescaler Assignment 0 assigns to Timer0.
Prescaler rate select ‘ 111 ’ – full prescaler, divide by 256.
Lesson 9 configures Timer0 with the prescaler for a maximum delay on Timer0. The
prescaler will divide the processor clock by 256 and Timer0 will divide that by 256
again. Thus, the Timer0 Flag will be set every 65536 μ s (0.0000001 second * 256 *
256), or about 15 times a second. The main program sits in a loop waiting for the
rollover and when it does, it increments the display and then loops back.
? 2007 Microchip Technology Inc.
DS41296B-page 27
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